1. Field of the Invention
The invention relates to a time interleaved analog-to-digital converter, and to a sorting method for operating this analog-to-digital converter.
2. Description of the Related Art
In modern data processing there is a need to process increasingly large amounts of data in shorter and shorter times and to condition it for further data communication. The respective electronic components, for example memory modules, processors and also logic components, such as PLDs or FPGAs, are therefore configured for increasingly high clock frequencies. As a result of this the analog-to-digital converters (ADC) which are present in such electronic components have correspondingly high sampling rates.
An analog-to-digital converter which has been gaining in importance recently owing to its high sampling rate is what is referred to as the time interleaved analog-to-digital converter (TIADC) in the relevant literature, or is termed a converter array for short. The design and the method of operation of such a time interleaved analogue, to digital converter, referred to below for short as TIADC, is described in Black, W. C., Hodges, D. A., Time Interleaved Converter Arrays, IEEE Journal of Solid-State Circuits, volume 15, number 6, pages 1022-1029, 1980.
In the simplest case, a TIADC has two analog-to-digital converters which are arranged in parallel with one another as a component of a converter array, said analog-to-digital converters carrying out alternate time interleaved sampling of a common analogue input signal and making it available in digital form. This parallel connection and the alternate operation of the converters which are arranged in parallel makes the sampling rate and conversion rate of the entire TIADC appear doubled compared to the sampling rate of the individual parallel ADCs. Generally, a TIADC may be composed of any desired number of ADCs which are arranged in parallel with one another.
FIG. 1 is a schematic circuit diagram showing the design of a known TIADC. The time interleaved ADC has a converter array with N ADCs 2-1 to 2-N which are arranged in parallel with one another and which are connected at the input ends to the input 4 and at the output ends to an input of a multiplexer 3. The analogue input signal XIN is fed to the individual ADCs 2-1 to 2-N, usually also referred to as ADC channels, said input signal XIN being sampled by the individual ADCs 2-1 to 2-N with a certain time offset and digitized. The individual digital signals of the ADCs 2-1 to 2-N are combined by means of the multiplexer 3 so that a higher sampling rate is effectively obtained for the digital output signal XOUT at the output 5. The effective sampling rate of the TIADC is ideally increased to N-times the sampling rate of an individual ADC 2-1 to 2-N.
The individual ADCs 2-1 to 2-N are arranged in a physically fixed fashion, that is to say can no longer be shifted, within the converter array after their manufacturing process. However, with such an array of individual ADCs 2-1 to 2-N there is a problem that any type of incorrect adaptation (mismatch) of the individual ADCs 2-1 to 2-N to one another leads to a conversion error which affects the output signal XOUT. Such incorrect adaptation may depend on various parameters which are briefly described below:
For example, when a plurality of individual ADCs 2-1 to 2-N are used within one converter array there is a time offset between the individual converters. A time offset is defined as a deviation from the ideal sampling time (also referred to as a delay mismatch, timing mismatch or aperture delay mismatch). Different time offset values of the individual ADCs 2-1 to 2-N lead however to an undesired interference spectrum in the output signal XOUT. For the frequency of this interference spectrum, the following relationship applies for a sinusoidal input signal with the frequency fe:±fe+(m*fs/N),where fs is the sampling frequency, N is the number of converters and m=[0 . . . N−1] is an integral multiple. Especially at high frequencies, the intervals or timing differences of adjacent converters become smaller and smaller so that the time offset problem becomes more and more pronounced here.
In the same way, differences in the amplification of the input signal lead to undesired additional spectrums whose frequency is however dependent on the input signal. Incorrect adaptations in the bandwidth of the individual parallel ADCs of the converter array typically give rise to undesired additional interference spectrums. Overall it is therefore to be noted that the individual parallel ADCs typically have usually small but different properties, which generally has a negative effect on the properties of the entire converter arrangement. In particular, any form of deviation in the transmission behaviour and thus in the transmission function of the individual AD leads to additional undesired interference spectrums in the output signal.
FIG. 2 shows the output spectrum PS of a time interleaved ADC for the case N=8, that is to say when 8 parallel ADCs are used. The reference number 6 refers to the input spectrum which is obtained from the conversion of the input signal XIN. This input spectrum 6 is predefined and does not change as a result of a change in the channel sequence. In addition to this input spectrum 6, additional spectrums 7 are also present, at the interval fs/N. These additional spectrums 7 which result from the abovementioned incorrect adaptations of the individual converters, constitute authentic copies of the input spectrum 6 which results from the input signal XIN and thus also contain the properties of the input signal XIN. The power which is contained in these additional spectrums 7 is, as illustrated in FIG. 2, distributed more or less randomly owing to the random incorrect adaptations and is also located in the region of the spectrum 6 for the input signal XIN. However, this is undesired, in particular if the power of these additional spectrums 7 in the region of the input spectrum 6 is very large.
The problem of incorrect adaptation, and in particular the incorrect adaptation resulting from different time offset values increases with increasingly small structure sizes such as are used in future manufacturing technologies in what is referred to as the deep submicron range with structure widths of less than 70 nm since absolute errors have increasingly serious effects there owing to the smaller structural widths. The need for power optimization of the individual ADCs of a time interleaved analog-to-digital converter is becoming more and more significant, in particular for these future manufacturing technologies.
The incorrect adaptations mentioned above can be avoided and/or reduced, on the one hand, by analogue circuit measures or by digital. standardization methods which will be described briefly below:
Analogue circuit measures for reducing incorrect adaptations entail a very high level of complexity of circuitry together with a very high power consumption, if such a reduction is at all possible, in particular when there are a plurality of individual ADCs of one converter array. These circuit measures are based on avoiding circuit errors by, for example, implementing very precise clock generation for the actuation of the individual ADCs of the converter array so that the time offset problem does not arise at all. In particular at very high frequencies this solution is however very difficult to implement at acceptable cost.
The digital standardization methods described, for example in Fu, D., Dyer, W. C., Lewis, S. H., Hurst, P. J., “A Digital Background Calibration Technique for Time Interleaved Analogue-to-Digital Converters,” IEEE Journal of Solid-State Circuits, volume 33, number 12, pages 1904-1911, 1988, and Jamal, S. M., Daihong, F., Chang, N. C. J., Hurst, P. J., Lewis, S. H., “A 10-b 120-{M}sample/s time-Interleaved analogue-to-digital converter with digital background calibration,” IEEE Journal of Solid-State Circuits, volume 37, number 12, pages 1618-1627, 2002, solve the problem of amplification adaptation (see Dyer et al.) and of the time offset in correct adaptation (see Jamal et al.). The precision of these digital methods depends however directly on how precise the respective parameter, that is to say the amplification and the time offset error, are determined, that is to say how precise the error identification is. In order to determine and thus also correct sampling time error adaptations there are currently only very costly numeric methods which are capable of being implemented with an exorbitantly high computational complexity, which far exceeds acceptable limits, in particular when a plurality of individual ADCs of one TIADC are used. Above all, the correction which has to take place during the ongoing operation of the TIADC constitutes a hurdle which is frequently impossible to overcome technically owing to the necessary computing power therefor. For this reason, this method of error compensation is frequently not practical.
For these reasons, an error reduction process, which is intended to reduce the effects of an incorrect adaptation, is very frequently performed. In documents Jin, H., Lee, E. K. F., Hassoun, M., “Time-Interleaved (A/D) Converter with Channel Randomization”, Proceedings of 1997 {IEEE} International Symposium and Circuits on Systems, volume 1, pages 425-428, 1997; Tamba, M., Shimizu, A., Munakata, H., Komuro, T., “A Method to Improve (SFDR) with Random Interleaved Sampling Method,” International Test Conference, Proceedings, pages 512-520, October 2001; and El-Sankary, K., Assi, A., Sawan, M, “New Sampling Method to Improve the (SFDR) of Time-Interleaved (ADCs),” Proceedings of the 2003 International Symposium on Circuits and Systems, volume 1, pages 833-836, 2003, algorithms and circuit arrangements are described which are intended to bring a certain degree of randomness into the sequence of the individual ADCs during the parallel operation of these ADCs and thus to distribute the error spectrum generated by the incorrect adaptation. This introduced randomness in the sequence of the individual ADCs brings about the uniform distribution of the spectral power arising over the entire frequency band due to incorrect adaptations. However, a problem with these methods is that there is no effective improvement achieved in the signal-to-noise ratio since the undesired power is in fact not eliminated but merely distributed uniformly. Furthermore, this random distribution, which will be referred to below for short as randomization, is based on a greater or smaller number of sampled values which are however not present in short messages or surge-like signals such as what are referred to as signal bursts. For this reason, with such short signals there is usually insufficient stochastic distribution of the converters. Moreover, with this randomization method there are also certain restrictions which result from the physical peripheral conditions of the operation of the converter (setup and hold times).